PQCInside: 超高吞吐多项式 NTT 硬件加速器、Keccak 算力核与全定制物理加固 IP

PQCInside 对外授权经过芯片流片实测验证、具备强侧信道防护能力的寄存器传输级 (RTL) 芯片 IP 核、自动化宏单元生成工具及面向台积电 (TSMC)、格芯 (GlobalFoundries) 与英特尔 (Intel) 制程节点的验证套件，助力芯片厂商将后量子算法硬化进量产商用 ASIC。

PQCInside Semiconductor IP Delivery & Verification Architecture

Synthesizable SystemVerilog RTL, automated DPA-hardened cell placer, and UVM verification suite

Central System: PQC Silicon IP Macro - FIPS 203/204 Hardened Core

Cryptographic Nodes

  • Synthesizable RTL Core
  • Foundry Macrocell Generator
  • Side-Channel Synthesis Plugin
  • UVM Verification Testbench
  • NIST CAVP Vector Suite

Architectural Layers & Protocols

  • Semiconductor RTL Source Plane (Fully Synthesizable SystemVerilog (IEEE 1800)): Providing parameterizable core architectures configurable for area, throughput, or ultra-low power.
  • Foundry Hardened Macrocells (GDSII Layouts for TSMC 16nm/7nm/5nm/3nm Nodes): Delivering silicon-verified physical layouts with pre-routed power grids and balanced differential clock trees.
  • Automated Side-Channel Shielding (Silicon Cell Placement Decorrelation Engine): Automating cell-level interleaving and dummy fill insertion to eliminate electromagnetic radiation peaks.
  • Turnkey Certification Collateral (Comprehensive UVM Testbenches & CAVP Vectors): Providing complete verification collateral and module security policies for rapid FIPS 140-3 certification.

Key Metrics: Silicon-Proven (Foundry Validation Status) | 3nm to 28nm (Supported Process Nodes) | 100% UVM (Functional Code Coverage) | Turnkey (CMVP Documentation Package)

后量子硅IP核心、自动化抗侧信道RTL综合器与加固型ASIC宏单元

深入剖析 NIST FIPS 203/204/205 标准、格密码学、侧信道攻击防护及后量子计算防御架构中的Post-Quantum Silicon IP Cores, Automated Side-Channel Resistant RTL Synthesizers & ASIC Hardened Macrocells关键工程实践。

Core Engineering Areas

Technical Articles

Related Cluster Architecture Specifications