Core engineering and protocols for Automated Side-Channel Synthesis.
Writing side-channel resistant RTL source code is necessary but insufficient: standard ASIC place-and-route tools (like Synopsys IC Compiler or Cadence Innovus) prioritize timing closure and wire congestion, often routing complementary differential wires with unequal lengths and parasitic capacitances, re-introducing power-analysis leakage on the manufactured chip.
PQCInside licenses specialized physical design scripts and DRC rule decks that guide commercial EDA tools during clock tree synthesis and cell placement. By enforcing symmetrical differential routing and automated dummy cell interleaving, the physical silicon retains its theoretical mathematical side-channel immunity.