Core engineering and protocols for Parameterizable Silicon IP.
Semiconductor architects face widely diverging constraints: a hyperscale cloud server processor (like AWS Graviton or Google Axion) requires millions of encapsulations per second and can afford large silicon die area, whereas a consumer smartwatch SoC is constrained to fractions of a square millimeter and milliwatts of power. PQCInside provides a single, fully parameterizable RTL codebase.
Using SystemVerilog configuration parameters, designers configure the number of parallel polynomial butterfly units (1, 2, 4, or 8), select between single-port or dual-port memory architectures, and enable or disable hardware masking pipelines. The automated build system produces optimized netlists tailored precisely to the customer's design constraints.